The present invention relates generally to the art of semiconductor devices and more particularly to methods and apparatus for monitoring plasma charging during semiconductor processing.
In the course of manufacturing semiconductor devices, certain processing steps involve the use of electrically charged plasma. Ion implantation, plasma etching, and other charged processing steps may damage semiconductor wafers, and the devices and circuits thereof. For instance, plasma dry etching operations employ an electrically excited gas etchant, where the surface to be etched is coated with a patterned layer of photoresist and then exposed to a gaseous plasma of the gas. Plasma dry etching is often used for controlled etching of high density features and is generally anisotropic, whereas wet etching techniques are commonly used to remove large volumes of material, being generally isotropic. Despite having certain advantages in many applications where anisotropic etching is desired, plasma etching can cause charge accumulation in semiconductor wafer workpieces being etched. The plasma is made up of a mix of charged particles, and there is a tendency for some such charged particles to accumulate on the wafer surface through what is sometimes referred to as the antenna effect.
This charge accumulation can lead to damage of transistors, gates, circuits, and other structures in the finished product. For example, plasma related charging can result where there are large antennas of conducting material such as metal or polysilicon in the workpiece, which may be electrically connected to transistor gates with thin gate oxide. Such antennas may collect a relatively high level of electrical charge by virtue of their large areas during plasma based processing operations. The collected charge may then be conducted through circuit paths in the wafer due to a voltage potential developed between the wafer surface and the underlying substrate material. This charge may thus be conducted to transistors or other devices in the wafer, resulting in performance degradation and/or damage thereto.
Various devices have thusfar been developed to measure the resulting voltage potential (or a current flow) between a charge collection area on the surface of the semiconductor device wafer and the substrate of the semiconductor wafer. Such devices include monitors or sensors located proximate the wafer workpieces during implantation or other processing steps involving plasma, which provide sensor signals to control systems or user interface devices. The actual charging of the semiconductor wafer is then inferred from the sensor signal. Other plasma charging measurement devices have been developed, which are formed directly in the wafer workpieces or in dedicated test wafers. These in-situ plasma charging sensors typically consist of dedicated memory cells, such as one or more electrically erasable programmable read only memory (EEPROM) cells formed in the wafer. For example, one or more such EEPROM memory cells may be provided, having a stacked gate MOS type transistor operating as voltage or current sensor.
In such memory type detector devices, a charge collection electrode is located on the top of the wafer, and is associated with the control gate of a stacked gate MOS type transistor, so as to collect plasma related charge during processing, which in turn affects the transistor gate. As plasma related charge is collected at the wafer surface, the transistor based memory cell measures the resulting voltage potential between the charge collection electrode and the wafer substrate. The voltage potential in the wafer, in turn changes the threshold voltage Vt of the memory cell, and hence the threshold voltage Vt thereof can be measured before and after a plasma related processing step. A comparison of the threshold voltage measurements is then used to estimate the plasma charging associated with the processing step. For instance, the threshold voltage shift of the sensing transistor may be used to calculate the plasma charging voltage during plasma processing.
More than one such charge monitoring devices are typically provided to monitor the wafer during fabrication and processing. A first or initial threshold voltage is programmed prior to exposing the wafer to a plasma related process, typically by probing the wafer and providing a known programming signal to the transistor via the charge collection electrode. At this point, the actual initial threshold voltage is sometimes measured or verified, prior to performing wafer processing steps involving plasma. After the processing step or steps of interest, the EEPROM transistor is probed and a second or final threshold voltage is measured. Once the initial and final threshold voltages are determined, then the surface potential related to the plasma can be estimated using a calibration curve or plot of threshold voltage shift versus gate voltage for the EEPROM transistor. In this regard, the estimated gate voltage represents the voltage potential between the charge collection electrode at the wafer surface and the wafer substrate. Where a resistance of known value is provided between the charge collection electrode and the substrate, then the plasma processing related current can be determined according to the gate voltage and the known resistance value. In this fashion, EEPROM transistor-based charge detection devices can be used to estimate the plasma related charging of a particular processing step.
However, these devices suffer from several shortcomings. For example, EEPROM memory cell type charging sensors are limited to detecting voltage, for example, in a range of about xe2x88x9225 to +30 volts. Consequently, these EEPROM type monitor devices are unable to quantify or measure plasma related potentials above this range. Furthermore, the threshold voltage of the EEPROM cell type detectors is sensitive to ultra-violet (UV) radiation. As a result, the threshold voltage shift represents both plasma process related charging and exposure of the wafer to UV sources during processing. Thus, it may be difficult or impossible to differentiate between the two in order to accurately quantify the plasma charging in the manufacturing process. Moreover, the construction of EEPROM memory cells is relatively complex, requiring the formation in the wafer of the source, drain, and gate structures of the MOS type transistor, thereby making the manufacturing process more difficult. Thus, there is a need for improved plasma charging monitor devices and methodologies by which plasma charging effects in semiconductor device manufacturing processes can be characterized, without the UV sensitivity and voltage range limitations associated with prior insitu and other charging sensors.
The following presents a simplified summary in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention relates to apparatus and methods for monitoring plasma related charging in a semiconductor wafer, by which the above mentioned and other shortcomings associated with the prior art may be mitigated or avoided. Ferroelectric (FE) capacitor plasma charging monitor devices are provided, which are relatively simple to design and fabricate in production and/or test wafers, and which do not suffer from the UV sensitivity problems associated with EEPROM type insitu monitors. In addition, the FE sensor devices are not limited by the voltage detection ranges achievable in prior transistor-based memory cell charging sensors. The invention can thus be employed to quantify plasma processing related charging effects associated with process steps, including for example, resist ashing operations, dielectric deposition operations, such as using plasma enhanced chemical vapor deposition (PECVD), metal or dielectric etch operations, such as dry plasma etching, implantation operations, and other process steps in which plasma is employed.
One aspect of the present invention relates to plasma charging monitors, comprising a ferroelectric (FE) capacitor formed in a semiconductor wafer between the top surface and the underlying substrate, an exposed conductive antenna, which is connected to a first or upper terminal or electrode of the FE capacitor, and a conductive probe pad connected to the other (e.g., lower) capacitor electrode. Ferroelectric materials exhibit electric polarization behavior, wherein the polarity can be reversed by application of a suitable electric field, such as by applying a voltage potential between the antenna and the wafer substrate material. Once a ferroelectric capacitor device is preprogrammed to a first polarity, application of a switching voltage value of opposite polarity will cause the capacitor polarity to change. Otherwise, once the external voltage is removed, the capacitor polarity returns to its original (e.g., preprogrammed) state. The sizes and configurations of the FE capacitor, the antenna, and resistances in the resulting series circuit can be selected so as to provide a desired switching voltage for the plasma charging monitor. The FE capacitor type plasma charging apparatus of the invention can thus be preprogrammed to a first polarity, and measured after intervening process steps, to ascertain if the charging related to the process steps exceeded the switching voltage for the monitor.
Ferroelectric materials can display a wide range of dielectric, ferroelectric, piezoelectric, electrostrictive, pyroelectric and electro-optical properties, and are similar to ferromagnetic materials in certain respects, such as regarding spontaneous polarization. The FE capacitor may be formed, for example, through metal organic chemical vapor deposition (MOCVD) using ferroelectric thin films such as Pb(Zr,Ti)O3 (PZT), (Ba,Sr)TiO3 (BST), SrTiO3 (STO) and SrBi2Ta2O9 (SBT), BaTiO3 (BTO), (Bil-xLax) 4Ti3O12 (BLT), or other ferroelectric material formed between two conductive electrodes in the semiconductor wafer. A resistor may be provided between the antenna and the capacitor, such as using doped polysilicon, in order to facilitate design of the series circuit for charging monitoring. The FE type capacitor may be preprogrammed via the antenna and the probe pad using an external instrument, for example, a voltage source, such that the FE capacitor attains a preprogrammed polarity. One or more processing steps are then performed, and the polarity of the FE capacitor is measured. A change in the FE capacitor polarity will thus indicate that wafer charging during the intervening processing step or steps exceeded a known value.
One or more such devices may be formed in the wafer, individually having different predetermined resistance values, capacitor sizes, and/or different antenna sizes. In this manner, plasma related charging during processing may cause polarity changes in some FE capacitors, and no polarity change in others. Knowing the circuit component values (e.g., resistances) for the devices experiencing a polarity change, and for those that did not, allows a determination of the plasma related charging voltage and/or current during processing. Polarity changes in individual devices can thus be indicative of plasma related charging above a certain level, and multiple devices associated with different predetermined levels can be used to provide an estimate of the charging current and/or voltage.
Because the FE type capacitor monitors are relatively insensitive to UV exposure, the polarity changes (e.g., or lack of polarity changes) therein are directly indicative of plasma charging exposure, regardless of any intervening UV experienced by the wafer. Furthermore, the FE capacitor type monitor devices according to the present invention do not suffer from the voltage range limitations of memory cell type devices. Moreover, the FE capacitor based charging monitor devices are simpler and easier to construct than EEPROM memory cell based monitor devices, which require formation of transistor drain/source regions, and gate structures in a wafer. The invention further provides techniques for making plasma charging monitors using FE capacitors in a semiconductor wafer.
Another aspect of the invention provides methods of monitoring plasma related charging in a semiconductor wafer, which mitigate the problems encountered with prior techniques. A ferroelectric capacitor in a semiconductor wafer is preprogrammed prior to performing a processing operation on the wafer. A post processing polarity associated with the FE capacitor is then measured, and plasma related charging associated with the processing operation is determined or estimated according to the measured polarity. For instance, a change in the FE capacitor polarity may indicate that wafer charging during the intervening processing exceeded a known value. The FE capacitor may be preprogrammed and subsequently measured by connection of external instrumentation (e.g., preprogramming sources and polarity detection devices, respectively) using probe points connected to the FE capacitor, one of which may be an exposed conductive antenna at the top surface of the wafer.
Preprogramming the capacitor may involve applying a voltage across the probe points so as to charge the ferroelectric capacitor to a first polarity. Subsequent to processing, a measurement instrument, such as a volt meter, can be connected across the probe points or pads, to measure the voltage polarity of the FE capacitor. If the post-processing capacitor polarity is different from the preprogrammed polarity, it can be discerned that the plasma charging exceeded a threshold value (e.g., current or voltage) corresponding to the physics of the charging monitor. If no polarity change is detected, it can be presumed that the plasma charging did not reach this threshold value. More than one such FE capacitor can be preprogrammed and subsequently measured, where a value of plasma charging current or voltage can be determined by comparing the polarity changes (e.g., or lack of polarity changes) in different FE capacitors, such as where different resistance values and/or different size antennas are associated with different FE capacitors.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.